CUDA Programming: A Developer's Guide to Parallel Computing with GPUsNewnes, 28 груд. 2012 р. - 600 стор. If you need to learn CUDA but don't have experience with parallel computing, CUDA Programming: A Developer's Introduction offers a detailed guide to CUDA with a grounding in parallel fundamentals. It starts by introducing CUDA and bringing you up to speed on GPU parallelism and hardware, then delving into CUDA installation. Chapters on core concepts including threads, blocks, grids, and memory focus on both parallel and CUDA-specific issues. Later, the book demonstrates CUDA in practice for optimizing applications, adjusting to new hardware, and solving common problems.
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З цієї книги
Результати 6-10 із 87
Сторінка 50
... usage can be swapped, giving 48 K of shared memory and 16 K of L1 cache. Going from 16 K of shared memory to 48 K of shared memory is a huge benefit for certain programs. Alignment requirements for optimal use became more strict than in ...
... usage can be swapped, giving 48 K of shared memory and 16 K of L1 cache. Going from 16 K of shared memory to 48 K of shared memory is a huge benefit for certain programs. Alignment requirements for optimal use became more strict than in ...
Сторінка 66
... usage includes when a GPU server or servers are shared by people who use it at different times, teaching classes, for example. You may also have remote developers who need to run code on specially set up test servers, perhaps because ...
... usage includes when a GPU server or servers are shared by people who use it at different times, teaching classes, for example. You may also have remote developers who need to run code on specially set up test servers, perhaps because ...
Сторінка 98
... idy 1⁄4 (blockIdx.y * blockDim.y) þ threadIdx.y; const unsigned int tid 1⁄4 idx þ idy * blockDim.x * gridDim.x; /* Fetch the data value */ No. of Threads Maximum Register Usage 192 16 20 24 98 CHAPTER 5 Grids, Blocks, and Threads.
... idy 1⁄4 (blockIdx.y * blockDim.y) þ threadIdx.y; const unsigned int tid 1⁄4 idx þ idy * blockDim.x * gridDim.x; /* Fetch the data value */ No. of Threads Maximum Register Usage 192 16 20 24 98 CHAPTER 5 Grids, Blocks, and Threads.
Сторінка 104
... usage is with sorted data. This provides a variation on the worst-case usage. Here one bank after another gets continuously hit with atomic writes, effectively serializing the problem. One solution is to step through the dataset such ...
... usage is with sorted data. This provides a variation on the worst-case usage. Here one bank after another gets continuously hit with atomic writes, effectively serializing the problem. One solution is to step through the dataset such ...
Сторінка 110
... usage of each of these in turn and how you can maximize the gain from using each type. Traditionally, most texts would start off by looking at global memory, as this often plays a key role in performance. If you get the global memory ...
... usage of each of these in turn and how you can maximize the gain from using each type. Traditionally, most texts would start off by looking at global memory, as this often plays a key role in performance. If you get the global memory ...
Зміст
Chapter 8 MultiCPU and MultiGPU Solutions | 267 |
Chapter 9 Optimizing Your Application | 305 |
Chapter 10 Libraries and SDK | 441 |
Chapter 11 Designing GPUBased Systems | 503 |
Chapter 12 Common Problems Causes and Solutions | 527 |
Index | 565 |
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CUDA Programming: A Developer's Guide to Parallel Computing with GPUs Shane Cook Обмежений попередній перегляд - 2012 |
Загальні терміни та фрази
256 threads algorithm allocate application array atomic atomic operations blockDim.x blockIdx.x bytes calculation compiler compute 2.x const int const u32 constant memory copy CUDA CALL cuda CUDA cores dataset device device_num elements example execution Fermi Figure function GB/s GeForce GTX 470:GMEM global memory GMEM hardware host memory ID:0 GeForce GTX InfiniBand instruction issue iterations Kepler kernel L1 cache latency Linux look loop malloc Memcpy memory access memory bandwidth memory fetch merge sort node num_elem num_elements num_threads number of blocks number of threads NVIDIA OpenMP operation optimization output Parallel Nsight parameter PCI-E performance pointer prefix sum problem processor radix sort reduce registers result serial shared memory SIMD simply single SP SP SP speedup stream synchronization Tesla threadIdx.x threads per block transfer typically uint4 unsigned int usage version is faster void warp write þ¼