CUDA Programming: A Developer's Guide to Parallel Computing with GPUsNewnes, 28 груд. 2012 р. - 600 стор. If you need to learn CUDA but don't have experience with parallel computing, CUDA Programming: A Developer's Introduction offers a detailed guide to CUDA with a grounding in parallel fundamentals. It starts by introducing CUDA and bringing you up to speed on GPU parallelism and hardware, then delving into CUDA installation. Chapters on core concepts including threads, blocks, grids, and memory focus on both parallel and CUDA-specific issues. Later, the book demonstrates CUDA in practice for optimizing applications, adjusting to new hardware, and solving common problems.
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Результати 6-10 із 53
Сторінка 93
... latency (the time it takes for a memory request to come back). Typically, latency to the global memory (DRAM) is around 400–600 cycles. During this time the GPU is busy doing other tasks, rather than idly waiting for the memory fetch to ...
... latency (the time it takes for a memory request to come back). Typically, latency to the global memory (DRAM) is around 400–600 cycles. During this time the GPU is busy doing other tasks, rather than idly waiting for the memory fetch to ...
Сторінка 94
... latency, to execute a given block is undefined. This is not good from a load balancing point of view. You want lots of threads available to be run. With 256 threads, 32 threads per warp give you 8 warps on compute 2.x hardware. You can ...
... latency, to execute a given block is undefined. This is not good from a load balancing point of view. You want lots of threads available to be run. With 256 threads, 32 threads per warp give you 8 warps on compute 2.x hardware. You can ...
Сторінка 105
... latency at the hardware level. A very high thread count per block is generally only useful where the threads in the block need to communicate with one another, without having to do interblock communication via the global memory. 5. The ...
... latency at the hardware level. A very high thread count per block is generally only useful where the threads in the block need to communicate with one another, without having to do interblock communication via the global memory. 5. The ...
Сторінка 107
... latency. Latency is the amount of time it takes to respond to a fetch request. This can be hundreds of processor cycles. If the program CUDA Programming. http://dx.doi.org/10.1016/B978-0-12-415933-4.00006-5 Copyright Ó 2013 Elsevier Inc ...
... latency. Latency is the amount of time it takes to respond to a fetch request. This can be hundreds of processor cycles. If the program CUDA Programming. http://dx.doi.org/10.1016/B978-0-12-415933-4.00006-5 Copyright Ó 2013 Elsevier Inc ...
Сторінка 108
... latency limited. To think of bandwidth and latency in everyday terms, imagine a supermarket checkout process. There are N checkouts available in a given store, not all of which may be staffed. With only two checkouts active (staffed), a ...
... latency limited. To think of bandwidth and latency in everyday terms, imagine a supermarket checkout process. There are N checkouts available in a given store, not all of which may be staffed. With only two checkouts active (staffed), a ...
Зміст
Chapter 8 MultiCPU and MultiGPU Solutions | 267 |
Chapter 9 Optimizing Your Application | 305 |
Chapter 10 Libraries and SDK | 441 |
Chapter 11 Designing GPUBased Systems | 503 |
Chapter 12 Common Problems Causes and Solutions | 527 |
Index | 565 |
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CUDA Programming: A Developer's Guide to Parallel Computing with GPUs Shane Cook Обмежений попередній перегляд - 2012 |
Загальні терміни та фрази
256 threads algorithm allocate application array atomic atomic operations blockDim.x blockIdx.x bytes calculation compiler compute 2.x const int const u32 constant memory copy CUDA CALL cuda CUDA cores dataset device device_num elements example execution Fermi Figure function GB/s GeForce GTX 470:GMEM global memory GMEM hardware host memory ID:0 GeForce GTX InfiniBand instruction issue iterations Kepler kernel L1 cache latency Linux look loop malloc Memcpy memory access memory bandwidth memory fetch merge sort node num_elem num_elements num_threads number of blocks number of threads NVIDIA OpenMP operation optimization output Parallel Nsight parameter PCI-E performance pointer prefix sum problem processor radix sort reduce registers result serial shared memory SIMD simply single SP SP SP speedup stream synchronization Tesla threadIdx.x threads per block transfer typically uint4 unsigned int usage version is faster void warp write þ¼