CUDA Programming: A Developer's Guide to Parallel Computing with GPUsNewnes, 28 груд. 2012 р. - 600 стор. If you need to learn CUDA but don't have experience with parallel computing, CUDA Programming: A Developer's Introduction offers a detailed guide to CUDA with a grounding in parallel fundamentals. It starts by introducing CUDA and bringing you up to speed on GPU parallelism and hardware, then delving into CUDA installation. Chapters on core concepts including threads, blocks, grids, and memory focus on both parallel and CUDA-specific issues. Later, the book demonstrates CUDA in practice for optimizing applications, adjusting to new hardware, and solving common problems.
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Результати 6-10 із 88
Сторінка 17
... hardware. While NVIDIA has a sizeable chunk of the GPU market, its competitors also hold a sizeable chunk. As developers, we want to develop products for as large a market as possible, especially if we're talking about the consumer ...
... hardware. While NVIDIA has a sizeable chunk of the GPU market, its competitors also hold a sizeable chunk. As developers, we want to develop products for as large a market as possible, especially if we're talking about the consumer ...
Сторінка 21
... hardware. Their goal was to achieve faster performance and often that was at the cost of portability. Feature X was implemented differently, or was not available in the next generation of parallel hardware. Periodically a revolutionary ...
... hardware. Their goal was to achieve faster performance and often that was at the cost of portability. Feature X was implemented differently, or was not available in the next generation of parallel hardware. Periodically a revolutionary ...
Сторінка 26
... hardware store. While fetching new tools the tradesperson is not working on the problem at hand. While this might seem bad, fetching data from a hard drive or SSD (solid-state drive) is akin to ordering an item at the hardware store. In ...
... hardware store. While fetching new tools the tradesperson is not working on the problem at hand. While this might seem bad, fetching data from a hard drive or SSD (solid-state drive) is akin to ordering an item at the hardware store. In ...
Сторінка 31
... hardware contains all the control logic for decoding many separate instruction streams. SIMD systems try to simplify this approach, in particular with the data parallelism model. They follow a single instruction stream at any one point ...
... hardware contains all the control logic for decoding many separate instruction streams. SIMD systems try to simplify this approach, in particular with the data parallelism model. They follow a single instruction stream at any one point ...
Сторінка 32
... hardware threads available. For the GPU, this is the number of SMs multiplied by the maximum load we can give to each SM, 1 to 16 blocks depending on resource usage. Notice we use the term logical and not physical hardware thread. Some ...
... hardware threads available. For the GPU, this is the number of SMs multiplied by the maximum load we can give to each SM, 1 to 16 blocks depending on resource usage. Notice we use the term logical and not physical hardware thread. Some ...
Зміст
Chapter 8 MultiCPU and MultiGPU Solutions | 267 |
Chapter 9 Optimizing Your Application | 305 |
Chapter 10 Libraries and SDK | 441 |
Chapter 11 Designing GPUBased Systems | 503 |
Chapter 12 Common Problems Causes and Solutions | 527 |
Index | 565 |
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CUDA Programming: A Developer's Guide to Parallel Computing with GPUs Shane Cook Обмежений попередній перегляд - 2012 |
Загальні терміни та фрази
256 threads algorithm allocate application array atomic atomic operations blockDim.x blockIdx.x bytes calculation compiler compute 2.x const int const u32 constant memory copy CUDA CALL cuda CUDA cores dataset device device_num elements example execution Fermi Figure function GB/s GeForce GTX 470:GMEM global memory GMEM hardware host memory ID:0 GeForce GTX InfiniBand instruction issue iterations Kepler kernel L1 cache latency Linux look loop malloc Memcpy memory access memory bandwidth memory fetch merge sort node num_elem num_elements num_threads number of blocks number of threads NVIDIA OpenMP operation optimization output Parallel Nsight parameter PCI-E performance pointer prefix sum problem processor radix sort reduce registers result serial shared memory SIMD simply single SP SP SP speedup stream synchronization Tesla threadIdx.x threads per block transfer typically uint4 unsigned int usage version is faster void warp write þ¼