CUDA Programming: A Developer's Guide to Parallel Computing with GPUsNewnes, 28 груд. 2012 р. - 600 стор. If you need to learn CUDA but don't have experience with parallel computing, CUDA Programming: A Developer's Introduction offers a detailed guide to CUDA with a grounding in parallel fundamentals. It starts by introducing CUDA and bringing you up to speed on GPU parallelism and hardware, then delving into CUDA installation. Chapters on core concepts including threads, blocks, grids, and memory focus on both parallel and CUDA-specific issues. Later, the book demonstrates CUDA in practice for optimizing applications, adjusting to new hardware, and solving common problems.
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Результати 6-10 із 87
Сторінка 50
... bytes. A cache line is the minimum amount of data the memory can fetch. Thus, if your program fetches subsequent elements of Copy To Device Kernel Copy From Device Copy To Device Kernel Copy From Device Copy To Device Kernel Copy From ...
... bytes. A cache line is the minimum amount of data the memory can fetch. Thus, if your program fetches subsequent elements of Copy To Device Kernel Copy From Device Copy To Device Kernel Copy From Device Copy To Device Kernel Copy From ...
Сторінка 51
... byte alignment of the dataset. However, if your program has a sparse and distributed memory pattern per thread, you need to disable this feature and switch to the 32-bit mode of cache operation. Finally, one of the last major changes we ...
... byte alignment of the dataset. However, if your program has a sparse and distributed memory pattern per thread, you need to disable this feature and switch to the 32-bit mode of cache operation. Finally, one of the last major changes we ...
Сторінка 66
... byte code where the target is a virtual architecture, and this is compiled to the actual target hardware at the point the program is invoked. The PTX JIT Table 4.1 Different CUDA File Types File Extension Meaning Processed By .cu Mixed ...
... byte code where the target is a virtual architecture, and this is compiled to the actual target hardware at the point the program is invoked. The PTX JIT Table 4.1 Different CUDA File Types File Extension Meaning Processed By .cu Mixed ...
Сторінка 79
... byte array size and change the kernel to invoke two blocks of 64 threads each as shown in Figure 5.8: some_kernel_func ... bytes, or 256 MB, of data storage space. Almost all GPU cards support at least this amount of memory space, so ...
... byte array size and change the kernel to invoke two blocks of 64 threads each as shown in Figure 5.8: some_kernel_func ... bytes, or 256 MB, of data storage space. Almost all GPU cards support at least this amount of memory space, so ...
Сторінка 85
... byte transaction instead of two, 64-byte transactions, due to accessing within a warp being coalesced and 128 bytes being the size of a cache line in the Fermi/Kepler hardware. In the square layout notice you have threads 0 to 15 mapped ...
... byte transaction instead of two, 64-byte transactions, due to accessing within a warp being coalesced and 128 bytes being the size of a cache line in the Fermi/Kepler hardware. In the square layout notice you have threads 0 to 15 mapped ...
Зміст
Chapter 8 MultiCPU and MultiGPU Solutions | 267 |
Chapter 9 Optimizing Your Application | 305 |
Chapter 10 Libraries and SDK | 441 |
Chapter 11 Designing GPUBased Systems | 503 |
Chapter 12 Common Problems Causes and Solutions | 527 |
Index | 565 |
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CUDA Programming: A Developer's Guide to Parallel Computing with GPUs Shane Cook Обмежений попередній перегляд - 2012 |
Загальні терміни та фрази
256 threads algorithm allocate application array atomic atomic operations blockDim.x blockIdx.x bytes calculation compiler compute 2.x const int const u32 constant memory copy CUDA CALL cuda CUDA cores dataset device device_num elements example execution Fermi Figure function GB/s GeForce GTX 470:GMEM global memory GMEM hardware host memory ID:0 GeForce GTX InfiniBand instruction issue iterations Kepler kernel L1 cache latency Linux look loop malloc Memcpy memory access memory bandwidth memory fetch merge sort node num_elem num_elements num_threads number of blocks number of threads NVIDIA OpenMP operation optimization output Parallel Nsight parameter PCI-E performance pointer prefix sum problem processor radix sort reduce registers result serial shared memory SIMD simply single SP SP SP speedup stream synchronization Tesla threadIdx.x threads per block transfer typically uint4 unsigned int usage version is faster void warp write þ¼