CUDA Programming: A Developer's Guide to Parallel Computing with GPUsNewnes, 28 груд. 2012 р. - 600 стор. If you need to learn CUDA but don't have experience with parallel computing, CUDA Programming: A Developer's Introduction offers a detailed guide to CUDA with a grounding in parallel fundamentals. It starts by introducing CUDA and bringing you up to speed on GPU parallelism and hardware, then delving into CUDA installation. Chapters on core concepts including threads, blocks, grids, and memory focus on both parallel and CUDA-specific issues. Later, the book demonstrates CUDA in practice for optimizing applications, adjusting to new hardware, and solving common problems.
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З цієї книги
Результати 6-10 із 59
Сторінка 27
... cache. In the shared memory case you tell the memory management unit to request this data and then go off and ... L1 and L2 caches. These can be configured with a preference toward cache or shared memory, allowing the programmer ...
... cache. In the shared memory case you tell the memory management unit to request this data and then go off and ... L1 and L2 caches. These can be configured with a preference toward cache or shared memory, allowing the programmer ...
Сторінка 32
... L1/L2/L3 cache on a CPU). Communication overhead typically scales badly and is often the bottleneck in poorly designed systems. The macro-level decomposition should be based on the number of logical processing units available. For the ...
... L1/L2/L3 cache on a CPU). Communication overhead typically scales badly and is often the bottleneck in poorly designed systems. The macro-level decomposition should be based on the number of logical processing units available. For the ...
Сторінка 44
... Memory (16x 1K) SM1 SM2 SM3 Constant Memory Bus Bus SM0 Global Memory Bus all MPs (64K) Optional SMn GPU #1 GPU #2 GPU #3 FIGURE 3.5 Block diagram of a GPU (G80/GT200) card. Global Memory L2 Cache Texture Cache Constant Cache L1 Cache.
... Memory (16x 1K) SM1 SM2 SM3 Constant Memory Bus Bus SM0 Global Memory Bus all MPs (64K) Optional SMn GPU #1 GPU #2 GPU #3 FIGURE 3.5 Block diagram of a GPU (G80/GT200) card. Global Memory L2 Cache Texture Cache Constant Cache L1 Cache.
Сторінка 45
... Cache L1 Cache Shared Memory Symmetric Multi-processor (SM) S pec ial F unct io n U nits (S FU ) L oad /S to re U nits (L S U ) N se ts of1 6 S Ps (C UD A C ore s) R egi ste rF ile FIGURE 3.6 Inside an SM. there is interpolation, for ...
... Cache L1 Cache Shared Memory Symmetric Multi-processor (SM) S pec ial F unct io n U nits (S FU ) L oad /S to re U nits (L S U ) N se ts of1 6 S Ps (C UD A C ore s) R egi ste rF ile FIGURE 3.6 Inside an SM. there is interpolation, for ...
Сторінка 49
... L1 cache memory on each SP. • Introduction of a shared L2 cache for all SMs. • Support in Tesla-based devices for ECC (Error Correcting Code)-based memory checking and error ... caches. The introduction of a cache Compute Levels 49.
... L1 cache memory on each SP. • Introduction of a shared L2 cache for all SMs. • Support in Tesla-based devices for ECC (Error Correcting Code)-based memory checking and error ... caches. The introduction of a cache Compute Levels 49.
Зміст
Chapter 8 MultiCPU and MultiGPU Solutions | 267 |
Chapter 9 Optimizing Your Application | 305 |
Chapter 10 Libraries and SDK | 441 |
Chapter 11 Designing GPUBased Systems | 503 |
Chapter 12 Common Problems Causes and Solutions | 527 |
Index | 565 |
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CUDA Programming: A Developer's Guide to Parallel Computing with GPUs Shane Cook Обмежений попередній перегляд - 2012 |
Загальні терміни та фрази
256 threads algorithm allocate application array atomic atomic operations blockDim.x blockIdx.x bytes calculation compiler compute 2.x const int const u32 constant memory copy CUDA CALL cuda CUDA cores dataset device device_num elements example execution Fermi Figure function GB/s GeForce GTX 470:GMEM global memory GMEM hardware host memory ID:0 GeForce GTX InfiniBand instruction issue iterations Kepler kernel L1 cache latency Linux look loop malloc Memcpy memory access memory bandwidth memory fetch merge sort node num_elem num_elements num_threads number of blocks number of threads NVIDIA OpenMP operation optimization output Parallel Nsight parameter PCI-E performance pointer prefix sum problem processor radix sort reduce registers result serial shared memory SIMD simply single SP SP SP speedup stream synchronization Tesla threadIdx.x threads per block transfer typically uint4 unsigned int usage version is faster void warp write þ¼