CUDA Programming: A Developer's Guide to Parallel Computing with GPUsNewnes, 28 груд. 2012 р. - 600 стор. If you need to learn CUDA but don't have experience with parallel computing, CUDA Programming: A Developer's Introduction offers a detailed guide to CUDA with a grounding in parallel fundamentals. It starts by introducing CUDA and bringing you up to speed on GPU parallelism and hardware, then delving into CUDA installation. Chapters on core concepts including threads, blocks, grids, and memory focus on both parallel and CUDA-specific issues. Later, the book demonstrates CUDA in practice for optimizing applications, adjusting to new hardware, and solving common problems.
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Сторінка vii
... 108 Types of data storage ........................................................................................ 110 Register Usage...................................................................................................
... 108 Types of data storage ........................................................................................ 110 Register Usage...................................................................................................
Сторінка ix
... ....................................................... 360 Strategy 4: Thread Usage, Calculations, and Divergence..................................... 361 Thread memory patterns.....................................................
... ....................................................... 360 Strategy 4: Thread Usage, Calculations, and Divergence..................................... 361 Thread memory patterns.....................................................
Сторінка 32
... usage. Notice we use the term logical and not physical hardware thread. Some Intel CPUs in particular support more than one logical thread per physical CPU core, so-called hyperthreading. GPUs run multiple blocks on a single SM, so we ...
... usage. Notice we use the term logical and not physical hardware thread. Some Intel CPUs in particular support more than one logical thread per physical CPU core, so-called hyperthreading. GPUs run multiple blocks on a single SM, so we ...
Сторінка 36
... usage. The available stack can be queried with API call cudaDeviceGetLimit() . It can also be set with the API call cudaDeviceSetLimit(). Failure to allocate enough stack space, as with CPUs, will result in the program failing. Some ...
... usage. The available stack can be queried with API call cudaDeviceGetLimit() . It can also be set with the API call cudaDeviceSetLimit(). Failure to allocate enough stack space, as with CPUs, will result in the program failing. Some ...
Сторінка 37
... usage of GPU accelerators (Figure 3.1). Notice that all GPU devices are connected to the processor via the PCI-E bus. In this case we've assumed a PCI-E 2.0 specification bus, giving an effective transfer rate of 5 GB/s. PCI-E 3.0 had ...
... usage of GPU accelerators (Figure 3.1). Notice that all GPU devices are connected to the processor via the PCI-E bus. In this case we've assumed a PCI-E 2.0 specification bus, giving an effective transfer rate of 5 GB/s. PCI-E 3.0 had ...
Зміст
Chapter 8 MultiCPU and MultiGPU Solutions | 267 |
Chapter 9 Optimizing Your Application | 305 |
Chapter 10 Libraries and SDK | 441 |
Chapter 11 Designing GPUBased Systems | 503 |
Chapter 12 Common Problems Causes and Solutions | 527 |
Index | 565 |
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CUDA Programming: A Developer's Guide to Parallel Computing with GPUs Shane Cook Обмежений попередній перегляд - 2012 |
Загальні терміни та фрази
256 threads algorithm allocate application array atomic atomic operations blockDim.x blockIdx.x bytes calculation compiler compute 2.x const int const u32 constant memory copy CUDA CALL cuda CUDA cores dataset device device_num elements example execution Fermi Figure function GB/s GeForce GTX 470:GMEM global memory GMEM hardware host memory ID:0 GeForce GTX InfiniBand instruction issue iterations Kepler kernel L1 cache latency Linux look loop malloc Memcpy memory access memory bandwidth memory fetch merge sort node num_elem num_elements num_threads number of blocks number of threads NVIDIA OpenMP operation optimization output Parallel Nsight parameter PCI-E performance pointer prefix sum problem processor radix sort reduce registers result serial shared memory SIMD simply single SP SP SP speedup stream synchronization Tesla threadIdx.x threads per block transfer typically uint4 unsigned int usage version is faster void warp write þ¼