CUDA Programming: A Developer's Guide to Parallel Computing with GPUsNewnes, 28 груд. 2012 р. - 600 стор. If you need to learn CUDA but don't have experience with parallel computing, CUDA Programming: A Developer's Introduction offers a detailed guide to CUDA with a grounding in parallel fundamentals. It starts by introducing CUDA and bringing you up to speed on GPU parallelism and hardware, then delving into CUDA installation. Chapters on core concepts including threads, blocks, grids, and memory focus on both parallel and CUDA-specific issues. Later, the book demonstrates CUDA in practice for optimizing applications, adjusting to new hardware, and solving common problems.
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Сторінка 28
... x SDK and requires certain OS/hardware/driver-level support. One of the ... 2 or 50% of the original time. We're still left with the worstcase time ... compute power is the access time for data. The idea of data-based parallelism is that ...
... x SDK and requires certain OS/hardware/driver-level support. One of the ... 2 or 50% of the original time. We're still left with the worstcase time ... compute power is the access time for data. The idea of data-based parallelism is that ...
Сторінка 49
... compute 1.1 devices were greatly reduced. This make the GT200 series ... 2.x hardware are as follows: • Introduction of 16 K to 48 K of L1 cache ... Compute 1.x hardware has no cache, except for the texture and constant memory caches. The ...
... compute 1.1 devices were greatly reduced. This make the GT200 series ... 2.x hardware are as follows: • Introduction of 16 K to 48 K of L1 cache ... Compute 1.x hardware has no cache, except for the texture and constant memory caches. The ...
Сторінка 94
... Compute Capability 1.0 1.1 1.2 1.3 2.0 2.1 3.0 64 67 67 50 50 33 33 50 96 100 100 75 75 50 50 75 128 100 100 100 100 ... 2.x hardware. You can schedule up to 24 warps (32 Â 24 1⁄4 768 threads) at any one time into a given SM for compute ...
... Compute Capability 1.0 1.1 1.2 1.3 2.0 2.1 3.0 64 67 67 50 50 33 33 50 96 100 100 75 75 50 50 75 128 100 100 100 100 ... 2.x hardware. You can schedule up to 24 warps (32 Â 24 1⁄4 768 threads) at any one time into a given SM for compute ...
Сторінка 100
... compute 2.x, hardware does not suffer with only being able to coalesce data from a half warp and can do full-warp coalescing. Thus, on the test device, a GTX460 (compute 2.1 hardware), the 32 single byte fetches issued by a single warp ...
... compute 2.x, hardware does not suffer with only being able to coalesce data from a half warp and can do full-warp coalescing. Thus, on the test device, a GTX460 (compute 2.1 hardware), the 32 single byte fetches issued by a single warp ...
Сторінка 105
... compute 2.x hardware. However, unlike the CPU, this cache line will likely be immediately consumed by the multiple threads. 4. During a syncthreads() operation, the entire block stalls until every one of the threads meets the ...
... compute 2.x hardware. However, unlike the CPU, this cache line will likely be immediately consumed by the multiple threads. 4. During a syncthreads() operation, the entire block stalls until every one of the threads meets the ...
Зміст
Chapter 8 MultiCPU and MultiGPU Solutions | 267 |
Chapter 9 Optimizing Your Application | 305 |
Chapter 10 Libraries and SDK | 441 |
Chapter 11 Designing GPUBased Systems | 503 |
Chapter 12 Common Problems Causes and Solutions | 527 |
Index | 565 |
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CUDA Programming: A Developer's Guide to Parallel Computing with GPUs Shane Cook Обмежений попередній перегляд - 2012 |
Загальні терміни та фрази
256 threads algorithm allocate application array atomic atomic operations blockDim.x blockIdx.x bytes calculation compiler compute 2.x const int const u32 constant memory copy CUDA CALL cuda CUDA cores dataset device device_num elements example execution Fermi Figure function GB/s GeForce GTX 470:GMEM global memory GMEM hardware host memory ID:0 GeForce GTX InfiniBand instruction issue iterations Kepler kernel L1 cache latency Linux look loop malloc Memcpy memory access memory bandwidth memory fetch merge sort node num_elem num_elements num_threads number of blocks number of threads NVIDIA OpenMP operation optimization output Parallel Nsight parameter PCI-E performance pointer prefix sum problem processor radix sort reduce registers result serial shared memory SIMD simply single SP SP SP speedup stream synchronization Tesla threadIdx.x threads per block transfer typically uint4 unsigned int usage version is faster void warp write þ¼